1. Technical Field
This disclosure relates to a semiconductor package, and more particularly, to a chip stack package having a reduced thickness, and a method of fabricating the chip stack package.
2. Description of the Related Art
As electronic devices, such as portable personal computers (PCs) and mobile telephones, get smaller and become multifunctional, by virtue of the rapid development of digital technology, they need smaller, lighter and higher capacity semiconductor devices. The integration density of a semiconductor device increases with the capacity of a semiconductor package. To achieve very high integration density, a stack package contains a plurality of stacked semiconductor chips mounted on a printed circuit board, resulting in one unit semiconductor chip package.
FIG. 1 is a cross-sectional view of a conventional chip stack package. Referring to FIG. 1, the chip stack package 100 includes a substrate 110. The substrate 110 includes first and second circuit patterns 111 and 113 respectively arranged on first and second surfaces of the substrate 110. An external connection terminal 120 is positioned on each of the second circuit patterns 113. A unit semiconductor chip 160 is mounted on the first surface of the substrate 110. The unit semiconductor chip 160 includes first and second semiconductor chips 140 and 150. The first semiconductor chip 140 is mounted on the first surface of the substrate 110 by a first adhesive 130, and the second semiconductor chip 150 is stacked on the first semiconductor chip 140 by a second adhesive 135.
The first and second semiconductor chips 140 and 150 are separated from a wafer in chip regions defined by a scribe region. The first and second semiconductor chips 140 and 150 are cut along a scribe line in the scribe region so as to have the same die size. The first semiconductor chip 140 includes first pads 143 arranged at edge portions of an active surface of the first semiconductor chip 140. The second semiconductor chip 150 includes second pads 153 arranged at edge portions of an active surface of the second semiconductor chip 150. The first pads 143 of the first semiconductor chip 140 are electrically connected to the first circuit patterns 111 of the substrate 110 through first wires 170. The second pads 153 of the second semiconductor chip 150 are electrically connected to the first circuit patterns 111 of the substrate 110 through second wires 175. The first and second semiconductor chips 140 and 150, and the first and second wires 170 and 175 are coated with a sealing portion, or encapsulant, 180 for protection from the external environment.
To fabricate the chip stack package 100, the first semiconductor chip 140 is adhered to the substrate 110 by the first adhesive 130, and a primary wire bonding process is performed to electrically connect the first pads 143 of the first semiconductor chip 140 to the first circuit patterns 111 of the substrate 110 through the first wires 170. Subsequently, the second semiconductor chip 150 is adhered to the first semiconductor chip 140 by the second adhesive 135, and a secondary wire bonding process is performed to electrically connect the second pads 153 of the second semiconductor chip 150 to the first circuit patterns 111 of the substrate 110 through the second wires 175.
In the chip stack package 100, a uniform distance must be maintained between the first and second semiconductor chips 140 and 150, due to a loop height of the first wires 170. Therefore, the thickness t1 of the second adhesive 135 between the first and second semiconductor chips 140 and 150 is increased, increasing the overall thickness of the package. In order to reduce the thickness of the package, the thickness of a sealing portion, or encapsulant, is reduced, a wafer is ground to reduce the thicknesses of the semiconductor chips, or a wire bonding method is modified. However, such methods cause warpage of the package or make the package difficult to handle in processing steps.
The process of fabricating the package is complicated, because the first semiconductor chip 140 is adhered to the substrate 110 and a primary wire bonding process is then performed, and the second semiconductor chip 150 is adhered to the first semiconductor chip 140 and a secondary wire bonding process is performed. Such a problem becomes worse as the number of semiconductor chips stacked on the substrate 110 is increased.